1. Field of the Invention
This invention relates to methods and apparatus for improving the efficiency in the use of and data transmission to, from and within the circuitry of computers, ASICs, optical devices, and other devices that are adapted to accept and operate on serial and parallel binary digital data, and specifically to such data in the form of datum segments that may vary in length and, among other forms, can be expressed by the formula nnnnnddd . . . , where the n's represent the binary code that expresses the bit length of the datum segment ddd . . . , the data so formed also providing security against the compromising of data.
2. Description of the Related Art
In the development of the computer art, data transfer has long been a critical issue. The speed of what would appear to be the fastest computer at present, as noted by Katie Greene in “Simulators Face Real Problems,” Science, Vol. 301, No. 5631, pp. 301-302 (18 Jul. 2003), is reported to be 35,860 gigaflops, but advances beyond that speed are said to be limited by the need to wait for data on which to operate. Two of the patents previously issued to this inventor, i.e., U.S. Pat. Nos. 6,208,275 and 6,580,378, as well as application Ser. No. 10/462,868 filed on Jun. 16, 2003, have addressed that data transfer process. Although that work was addressed generally to the transfer of data to and from a computer, the methods and apparatus described are equally applicable to processes occurring entirely within a computer. The present invention continues that development and sets out, in one aspect of seeking faster computer operations, another step in the creation of systems by which data can be provided more efficiently, more rapidly, and with less waste of bit space both to/from and within a computer or like device. In this description, a “datum segment” is simply an amount of sequential binary code that represents an item of information.
U.S. Pat. No. 6,208,275, issued to this inventor on Mar. 27, 2001, shows a concatenator that accepts a series of datum segments of a fixed size, such as 8-bit bytes, and then concatenates them together to form larger words of lengths that would be an integral multiple of that fixed size, thereby to yield words of 16, 24, 32 bits, etc. The reason for so doing is that in a computer having, e.g., 32-bit data busses, it is wasteful of space to use such a bus to transmit a datum segment only 8 bits long—24 bit spaces are unused. The '275 concentrator serves to “string together” four 8-bit bytes and then transmit the resultant 32-bit data string, thus to use the full capacity of the bus so that one transmission does what would otherwise have taken four. No data transmission occurs during the actual concentration process, but that gate-based process will ordinarily be much faster than the data transfer, hence there is a net saving of time. Of course, the same principles will apply to other fixed byte or bus sizes such as 64-bit, 128-bit, etc.
U.S. Pat. No. 6,580,378, issued to this inventor on Jun. 17, 2003, sets out a simple data enumerator that counts the bytes on which the concentration process just noted is carried out, and “tags” each such byte with an index number. Those numbers will identify which positions within a destination register will contain which datum segments. When those datum segments are transmitted to a computer, those numbers also aid in recovering the original datum segments from the longer, concentrated data segments in the computer. The nnnnn bit count code is used in the present invention to aid in specifying the starting addresses of successive datum segments in the output register of the apparatus and in the computer or other device to which these data are to be sent, since, when treating variable length datum segments, those addresses will no longer be fixed in advance by a fixed datum segment size.
Application Ser. No. 10/462,868, filed Jun. 16, 2003, describes another method by which bit space can be saved in transmitting and using bit strings, in part by snipping therefrom any leading zeroes that take up space but do not convey any information. A second aspect of the apparatus is that it can treat datum segments of varying length, that might have come about either as a result of that zero-stripping process, or such datum segments may have been provided to the apparatus originally. Included is a general method of forming and using datum segments of varying length, by way of variable length shift register that can yield versions of all of the basic gates of digital electronics, e.g., AND, OR XNOR, etc., that can also be of varying length. By a “variable length” gate is meant that only those bit spaces in a register that correspond in number to the bit length of a datum segment at hand need to be utilized, thus leaving other adjacent bit spaces for other uses. It is one specific purpose of the present invention, that would not otherwise be available, to provide means by which datum segments, fixed-length bytes, identifiable bit sequences or data in any other form under whatever name, that could have been zero-stripped to include only meaningful data bits, can then be processed as such, as a matter of routine, thereby to maximize the data handling capabilities of such a system relative to any other system.
The processes of the Ser. No. 10/462,868 lead to a form of encoding a datum segment as nnnnnddd . . . , where nnnnn, the “bit count code”, expresses the number of bits in the datum segment that immediately follows, and the ddd . . . represent the actual bits of the datum segment. That method of expressing the nature of the datum segment comes about firstly by independently establishing the number of bits in the datum segment, which the apparatus of the 'xxx patent carries out. The actual code of the datum segment itself is then established and concentrated onto the bit code nnnnn, using 5 bits as an example. Concentration of this type could be carried out in the apparatus of the 'xxx patent since there, as here, the number of bits “n” used to express the number of bits in the datum segment was fixed, and since the datum segment ddd . . . is concentrated onto the Least Significant Bit (LSB) end of the nnnnn code, the length of the datum segment itself does not affect the concentration process.
An initial address is used for placement of the bit count code nnnnn, itself again having 4 bits, and the first bit of the datum segment is then placed at the address that immediately follows the code nnnnn, i.e., in the example using the 5-bit nnnnn code at the 5th register position. It is then necessary only to place that entire bit string into a register large enough to accommodate that entire nnnnnddd . . . code. The reason that the bit count code nnnnn is retained is to permit structuring of the circuitry within the computer to which these data are to be sent.
However, it is not immediately possible in the apparatus of the 'xxx patent to concentrate onto a first nnnnnddd . . . code a second such code, since the end point of that first nnnnnddd . . . datum segment will not be known, except indirectly through knowledge of the nnnnn value that is associated with each datum segment. What is needed is thus a means by which the position of the last bit of a variable length datum segment can be established with the hardware itself, so as not only to carry out concentrations of the form nnnnn+dddddd=nnnnndddddd as is done by the apparatus of the '275 patent, where here “+” means a concentration and “=” means that the result of that concentration then follows, but to concentrate those resultant terms, i.e., in concentration of the form nnnnnddd . . . +nnnnnddd . . . +nnnnnddd . . . =nnnnnddd . . . nnnnnddd . . . nnnnnddd . . . where the number of data bits “d” and hence the length of the datum segment as a whole can vary, and of course the ellipses would no longer be present, but the numbers of “d's” that represent the actual number of bits in each datum segment would be shown instead.
For example, and for brevity using here a bit count code of 4 bits, a resultant code for three datum segments of varying size could come out to be as0100110111001001100101111001100110101, which is an unambiguous encoding of the result of concatenating a 4-bit and a 12-bit datum segment together, and then concatenating a 9-bit datum segment onto that result, together with the content (selected arbitrarily) of each of them. In the above code, the initial 0100 bit count code identifies a following 4-bit datum segment; the code 1101 is the datum segment itself, the next bit count code 1100 identifies the 12-bit datum segment 100110010111, and the following 1001 bit count code then identifies a 9-bit datum segment which has been given the content 100110101. The present invention will construct an extended series of such variable and unpredictable length datum segments to encompass as much as possible of a data transfer bus and of the registers through which the datum segments may pass.